Author : Prof. R.Reis
Full Professor
Instituto de Informática
Universidade Federal do Rio Grande do Sul (UFRGS)
Porto Alegre, Brazil.
Full Professor
Instituto de Informática
Universidade Federal do Rio Grande do Sul (UFRGS)
Porto Alegre, Brazil.
BIOGRAPHY
Ricardo Reis was born in Cruz Alta, Brazil. He received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul(UFRGS), PortoAlegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Since 1981, he is a professor at the Informatics Institute of Federal University of Rio Grande do Sul, and a leader of the Microelectronics Group. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 400 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He received the 2015 IEEE CASS Meritorious Service Award. He was vice- president of CASS for two terms (2008/2011), representing R9. He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011 and 2012, and R9 Chapter of The Year 2013 and 2014. He is a founder of several conferences like SBCCI (sponsored by CASS in Brazil) and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/CEDA VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and Chair of IFIP TC10. He also launched EMicro, an annually microelectronics school in South Brazil, that now is co-sponsored by IEEE CAS chapter. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. Ricardo has also being participating in many Latin-American research activities. Prof. Reis is a member of the IEEE since 1981 and senior member since 2006. He is also member of the ACM, founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society).
Ricardo Reis was born in Cruz Alta, Brazil. He received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul(UFRGS), PortoAlegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Since 1981, he is a professor at the Informatics Institute of Federal University of Rio Grande do Sul, and a leader of the Microelectronics Group. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 400 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He received the 2015 IEEE CASS Meritorious Service Award. He was vice- president of CASS for two terms (2008/2011), representing R9. He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011 and 2012, and R9 Chapter of The Year 2013 and 2014. He is a founder of several conferences like SBCCI (sponsored by CASS in Brazil) and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/CEDA VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and Chair of IFIP TC10. He also launched EMicro, an annually microelectronics school in South Brazil, that now is co-sponsored by IEEE CAS chapter. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. Ricardo has also being participating in many Latin-American research activities. Prof. Reis is a member of the IEEE since 1981 and senior member since 2006. He is also member of the ACM, founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society).
"Low Power Challenges in IoT and CPS"
ABSTRACT
The increasing number of devices connected to the internet is providing the concept of Internet of Things, that together with Internet of Health, Internet of People and Internet of Something is constructing the Internet of Everything (IoE). There is also an overlapping between IoT and CPS (Cyber Physical Systems) that have as components not only electronic ones, but also mechanical components, optical components, organic components, chemical components, etc. A keyword in IoT is optimization, mainly power optimization. Power optimization must be done in all levels of design abstraction, and at physical level is related to the number of transistors. Also, many systems are critical ones, like in Internet of Heath, where reliability is a major issue. Most of the circuits designed nowadays use much more transistors than it is needed. The increasing leakage power and routing issues are an important reason to optimize the number of transistors, as leakage power is related to the number of transistors. Also, the replacement of a set of basic gates by a complex gate reduces the number of connections to be implemented using metal layers as well the number of vias. The reduction of the number of connections to be implemented using metal layers helps to improve routing and also helps to improve reliability. To cope with this goal, it is needed to provide tools to automatically generate the layout of any transistor network.
The increasing number of devices connected to the internet is providing the concept of Internet of Things, that together with Internet of Health, Internet of People and Internet of Something is constructing the Internet of Everything (IoE). There is also an overlapping between IoT and CPS (Cyber Physical Systems) that have as components not only electronic ones, but also mechanical components, optical components, organic components, chemical components, etc. A keyword in IoT is optimization, mainly power optimization. Power optimization must be done in all levels of design abstraction, and at physical level is related to the number of transistors. Also, many systems are critical ones, like in Internet of Heath, where reliability is a major issue. Most of the circuits designed nowadays use much more transistors than it is needed. The increasing leakage power and routing issues are an important reason to optimize the number of transistors, as leakage power is related to the number of transistors. Also, the replacement of a set of basic gates by a complex gate reduces the number of connections to be implemented using metal layers as well the number of vias. The reduction of the number of connections to be implemented using metal layers helps to improve routing and also helps to improve reliability. To cope with this goal, it is needed to provide tools to automatically generate the layout of any transistor network.
"Visualisation Tools"
ABSTRACT
The talk will show how we can use visualization tools to see how well our EDA tools and algorithms are running. For example, we use visualization tools to see how to improve our algorithms and tools for placement and routing. The talk will also include several uses of visualization tools to help the improvement of EDA tools as well the IC design flow.
The talk will show how we can use visualization tools to see how well our EDA tools and algorithms are running. For example, we use visualization tools to see how to improve our algorithms and tools for placement and routing. The talk will also include several uses of visualization tools to help the improvement of EDA tools as well the IC design flow.
"IC Design and EDA : a bit of History"
ABSTRACT
It will be presented some historical aspects of IC Design and the evolution of Design Automation. It will include some interesting strategies used in first microprocessors (several of them used still today) as well some strategies used in the Z8000 that were possible to get by doing reverse engineering. It will also be presented the methodologies used in the reserve engineering process, as well some highlights and strategies used in past EDA tools, some of them still being used.
It will be presented some historical aspects of IC Design and the evolution of Design Automation. It will include some interesting strategies used in first microprocessors (several of them used still today) as well some strategies used in the Z8000 that were possible to get by doing reverse engineering. It will also be presented the methodologies used in the reserve engineering process, as well some highlights and strategies used in past EDA tools, some of them still being used.
"Trends on EDA"
The design quality of modern chips depends on the quality of the EDA tools used in the design. With the evolution of nanotechnologies new EDA tools are needed. It will be presented some trends on EDA to cope with the evolution of manufacturing processes. Nowadays, an important set of tools are the ones to reduce power consumption in all abstraction levels of a design. A keyword in the design of nanochips is optimization. Also, the use of visualization tools is a key step in the development of EDA tools
